Optimization And Experimental Verification Of LDMOS Device With Surface Sub-micron Superjunction

The Lateral Double-Diffused MOSFET(LDMOS)is widely used in integrated circuits such as Alternating Current-Direct Current(AC-DC)circuits,Low Dropout Regulator(LDO)circuits,and high-voltage gate drivers due to its excellent performance.As the core switching device of high-voltage integrated circuits,keeping high breakdown voltage(V_B)and reducing the specific on-resistance(R_on,sp)is the main research direction of LDMOS devices.In order to improve the performance of LDMOS devices,a variety of optimized designs have been proposed,the most representative of which is the Super-Junction(SJ)structure.The voltage-sustaining layer is composed of alternately arranged junction voltage-sustaining layers consisting of N pillar and P pillar instead of the original single resistive voltage-sustaining layer.A new depletion mechanism is introduced into the devices,which allows the drift region achieve highly doping.The appearance of super-junction breaks the contradictory relationship between breakdown voltage and specific on-resistance.For lateral devices,the length of the super-junction determines its maximum breakdown voltage.At the same time,the narrower width of the super-junction achieves a higher concentration,and decide the specific on-resistance.Following this design concept,this thesis introduces the sub-micron super-junction into the LDMOS device which enables the lateral super-junction device achieves a lower specific on-resistance while having higher breakdown voltage.The main research contents are as follows:First,the submicron super-junction device structure is proposed and the optimization method of submicron super-junction is deduced.In terms of device structure,on the basis of the traditional LDMOS structure,the P buried layer and the N buried layer are sequentially implanted with high energy to form a micron-scale super-junction in the body.Before the introduction of the surface super-junction,the substrate-assisted depletion effect of the device is eliminated by using the internal super-junction to achieve ideal substrate conditions.And then the N-top layer and the P-top layer are injected to form a surface submicron super-junction.The surface submicron super-junction provides a low resistance current path on the surface of the device,which reduces the specific on-resistance of the device.The global normalization method is used to optimize the lateral super-junction,and the best power figure of merit model is derived as a theoretical guide for submicron super-junction.The optimal super-junction concentration can be obtained at a given super-junction length and width.Second,the simulation optimizes the process flow and key parameters of the submicron super-junction.The optimization of the device process steps was carried out to explore the influence of thermal processes on the super-junction morphology.Evaluating the current-carrying capability before and after the introduce of submicron super-junctions with normalized current-carrying capability.Then,the internal micron super-junction and the surface submicron super-junction are optimized guided by the equivalent substrate model and the highest FOM model.The optimized parameters of the device are obtained.On this basis,the high electric field peaks at the bird's beak region and the gate polycrystal due to the introduction of the surface super-junction are optimized to avoid premature breakdown of the device at this position.Finally,the device structure is verified experimentally.Based on the 500?700 V BCD process of the partner company combined with the optimization results of simulation,the device layout drawing and experimental verification were carried out.A submicron super-junction device with a super-junction width of less than 1?m was experimentally developed.The experimental results show that the breakdown voltage of the submicron super-junction device V_B=622.9 V,the specific on-resistance R_on,sp=28.1m?·cm~2,and the power figure of merit FOM reaches 13.8 MW/cm~2.Under the same breakdown voltage level,the specific on-resistance is 61.4%lower than the theoretical"silicon limit"of Triple RESURF.