Research Of Figure-of-merit Model And Device Structures For Shield-gate VDMOS

The power MOSFET?Metal Oxide Semiconductor Filed-effect Transistor?has excellent switching performance,high input impedance,and superior thermal stability,which has attracted much attention in smart power integrated circuits such as power management.Nowadays,the terminal markets including new energy vehicles,industrial automation,and Internet of Things devices have higher performance requirements for power MOSFET devices.The separated electrode of SG VDMOS?Shield-gate Vertical Double-diffused Metal Oxide Semiconductor?lead to the advantages of low R_on,sp?Specific On-resistance?and low Q_g?Gate Charge?.On the one hand,the buried electrode assists in depleting the drift region as a polysilicon field plate extending into the trench,so that the drift region electric field distribution could be optimized.On the other hand,the reducing overlap area between the gate electrode and the drain electrode results in the gate-drain capacitance reducing.Researchers at home and abroad conduct In-depth study of work characteristics,implementation process,new structure of SG VDMOS.However,there is still no perfect model to combine the three most important parameters including Breakdown voltage V_B,the Specific on-resistance R_on,sp and the Gate charge Q_g,and there is no complete theory to guide the design of SG VDMOS.The main innovations,main work contents and main conclusions of this topic are as follows:First,a minimum optimal value FOM model for shielded gate VDMOS devices is established in this paper,which can be used to guide the minimum FOM design of such devices under given process conditions.Specifically:First,SG VDMOS is abstracted as a small-size vertical device with VFP?Vertical Field Plate?.And the off-state electric field distribution of such devices is studied,and the expression of electric field in the drift region of such devices is obtained under the new boundary conditions,which can be well matched with the simulation results.Second,based on the expression of electric field distribution in the drift region,the new ENBULF?ENhanced BULk Field?condition is proposed connecting the actual manufacturing process and the tolerance,where the expression of optimal concentration in drift region is obtained by means of mathematical tools.Third,the concept of intrinsic gate charge Q_I?Intrinsic Gate Charge?is proposed,which can transform the complex capacitance of SG VDMOS devices into the device size and research the optimal FOM variation rules of devices without paying attention to the specific value of gate charge.Based on the concept of Q_I,it is the expression of the device's optimal FOM and the optimization function f which are consistent with the variation rule of the device's FOM that could be obtained.With the optimization function f and mathematical software,the design formula of W_S with the lowest FOM can be obtained.Second,based on the established minimum FOM model,two methods are proposed to optimize the device.It includes setting multi-layer epitaxy layer to optimize the electric field distribution in drift region to improve breakdown voltage and setting Nbuffer layer at the junction of channel and drift region to reduce R_on,sp.The simulation results show that the two methods are effective.Third,the minimum optimal FOM design of SG VDMOS devices is realized and experiment based on the proposed minimum FOM model.Two design formulas for the width of the silicon layer and the concentration of the drift region proposed by the minimal FOM model are used to obtain the optimal silicon width and the corresponding optimal drift concentration under given process conditions.The experimental results of the SG VDMOS device obtained based on this design shows that the SG VDMOS device with a breakdown voltage of 35 V owns a Specific On-resistance R_on,sp of 4.4 m??mm²,which is lower than the conventional 1-D silicon limit by 28.6%,and the gate-to-drain charge Q_gd is only 11.2 nC.