A Research On Chip Physics Features Analysis And Hiding Methods Of Hardware Trojan

Integrated circuit chip is the cornerstone of social informatization,industrial modernization and intelligent life.Electronic equipment with chip has already entered all aspects of human production and life.At present,the semiconductor supply chain presents the trend of globalization,and all links of chip manufacturing are scattered,which poses a great challenge to the security of chips.In recent years,chip security issues have emerged one after another.Chip powers around the world have continued to make efforts in the field of hardware security.They have not only enhanced the security of chips through detection methods,but also made many achievements in the design,implantation and concealment of Hardware Trojans,which has enhanced the aggressiveness of Hardware Trojans.In 2017,Shakya et al.^[1]of the University of Florida designed different types of Hardware Trojans.On this basis,they combined with a series of standard circuits to develop a standard test-set named Trusthub,which is the most widely used test-set in the field of Hardware Trojans.At present,there is no hardware security test set similar to Trusthub in China.In addition,the test benchmarks in Trust Hub are old and incomplete.With the continuous development of Hardware Trojan detection methods,Trust Hub can no longer meet the increasing requirements of detection accuracy.Therefore,based on the analysis of the physical field characteristics of the chip,this thesis studies the hardware hiding method of Hardware Trojan on layout level,which can not only improve the aggressiveness of Hardware Trojan,but also provide a better Hardware Trojan test-set and promote the development of Hardware Trojan detection methods.Based on the analysis and overview of the basic concept,structure,types and common design methods of Hardware Trojan,the main contents of this thesis are as follows:(1)A physical field sensitivity design method for chip layout is proposed in this thesis.Focusing on the layout implantation selection of Hardware Trojan,this thesis proposes a physical-field sensitivity design method of chip layout.According to the specific process of chip design,this thesis analyzes the physical resources such as layout space and wiring channel used in the physical design stage of the chip.Combined with the physical field side-channel characteristics such as the power consumption of the finished chip,the concept of physical field sensitivity of chip layout is proposed in this thesis.The sensitivity index comprehensively analyzes the layout space margin,wiring channel margin and the proportion of Hardware Trojan power consumption.It not only describes the sensitivity of a specific area of the chip when implanted by the Hardware Trojan,but also provides a reference for the selection of the placement position of the Hardware Trojan.(2)Two layout-level hardware trojan hiding algorithms are designed in this thesis.Aiming at the problem of Hardware Trojan embedding and hiding at layout level,this thesis designs two layout level Hardware Trojan hiding methods,based on the analysis of chip layout physical field sensitivity index.Firstly,this thesis analyzes the topology of the chip layout and adopts a Hardware Trojan sequential implantation method.On this basis,by measuring the degree of offset of the original layout,this thesis further proposes an optimal solution search algorithm based on global analysis.Then,this thesis analyzes the layout conflict and overlap area of the Hardware Trojan in the global effective position and the original layout device,and proposes the iterative implantation method of the Hardware Trojan optimization with minimal occlusion.Finally,an experimental example based on the reference circuit is set up.In the thesis,DBSCAN detection method and SOM detection method are used to detect the layout before and after the Hardware Trojan is hidden.The experimental results show that the two hiding methods proposed in this thesis have completed 100%hardware trojan hiding.