Design Of 40 Gb/s PAM4 Optical Interconnect Reconfigurable Transmitter Chip Based On DSP-DAC Architecture

Optical interconnection is the one way of Optical communication,which uses fiber to transfer and swap the high speed data.Compared with the electrical interconnection,Optical interconnection has the advantage of high bandwidth,low loss,free crosstalk,electromagnetic match.Therefore,Optical interconnection has been used widely in high performance computer groups,large scale data center,low delay communication and other high speed and high performance interconnection fields.It has broad application prospects.Due to the advantage of low cost,Intensity Modulated-Direct detection technology and Four level pulse amplitude modulation code have been considered as one of hot scheme in the short optical interconnection systems.The short optical interconnection system based on the Intensity Modulated-Direct detection usually uses low cost optical-electrical modulator and driver.However,Inter Symbol Interference and nonlinear maybe happen due to its limited bandwidth and linearity.It will decrease the performance of optical interconnection system.So,it is necessary to predistortion the data in the transmitter chip to eliminate the effect of Inter-Symbol-Interference and nonlinear.At present,the transmitter chip architecture is hard to reconstruct equalization information and realize nonlinear predistortion in real time.To solve this problem,this paper studies the transmitter chip architecture and equalization scheme of optical interconnection system,and strives to achieve nonlinear predistortion while reducing the complexity of the chip architecture and improving the flexibility of the architecture.The research work is as following :1)A 40 Gb/s optical interconnect reconfigurable transmitter chip architecture based on look-up table equalization and digital-to-analog converter is designed,and the feasibility analysis and specific circuit realization of the architecture are studied.The architecture uses a look-up table to read the equalized data that can be updated in real time,and finally transmits the analog signal to the channel through the digital-to-analog converter,so it can realize the reconstruction of the equalized data.The reconfigurable parameters include the number of linear FFE taps and the pre-equalizer mode(linear/non-linear pre-equalization mode),and the non-linear pre-equalization of the signal can be realized by writing the non-linear equalization data into the look-up table.2)Design the key circuit modules of transmitter chip.According to the structure and function of transmitter,high speed look-up table,high speed 4:1 serializer,pre-driver and high speed driver based on DAC are designed respectively.The high speed multiplexer based on dynamic latch is explored,and the pre-driver based on feedback resistor is studied.It is found that the resistor can decrease the Inter-Symbol-Interference effectively in the high speed links.3)The layout of key circuit modules is designed,and post layout simulation is finished.The simulation result shows that the designed transmitter can transmit 40 Gb/s PAM4 signal.