Fast Implementation Of SIKE Protocol Based On C Language And RISC-?

Due to the fast development of quantum-computers in recent years,post-quantum encryption emerges as the times require.In the process of post-quantum cryptography standardization held by the NIST(National Institute of Standards and Technology),supersingular isogeny key encapsulation protocol(SIKE)has survived from the third round of fierce competition because of its smaller key size and compatibility with traditional ECC encryption.Although researchers have done a lot of researches and efforts,the computation latency is still more than one order of magnitude slower than other popular candidates.In the latest implementation of SIKE,Montgomery representation is used for basic arithmetic operations over finite fields,because its corresponding reduction algorithm is widely considered to be the fastest modular reduction algorithm.In this paper,we propose a new data representation method based on unconventional radix,which can be used in supersingular isogeny-based crypto-systems,of which the SIKE is a subclass.The new representation can achieve faster modular reduction than Montgomery reduction algorithm,and other finite field algorithms can also benefit from it.Based on this representation,all basic arithmetic operations over finite field are implemented in C language and applied to the latest SIKE software library.The experimental results show that on the 64-bit operating system of Intel Xeon E5-2690 processor,the performance of SIKEp434,SIKEp503,SIKEp610 and SIKEp751 achieve 1.48x? 1.61x? 2.03 x and 1.65 x speedup compared to the state-of-the-art generic implementation.In addition,this paper implements the basic field arithmetic operations of the SIKE protocol using RISC-? based on the new data representation method.Compared with the C language implementation,about 3.2 times speedup was obtained.Moreover,based on the pure RISC-? assembly implementation,this paper explores the software-hardware co-design on Rocket Chip,a platform using RISC-? ISA.By expanding the instruction set of RISC-? to fit the inserted hardware accelerators.We have accomplished a hardware-software co-design system and achieved the performance improvement.