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Research And Design Of Convolutional Neural Network Accelerator Based On Multi-FPGA Co-acceleration

Posted on:2022-02-26Degree:MasterType:Thesis
Country:ChinaCandidate:Y WuFull Text:PDF
GTID:2518306575972289Subject:Computer technology
Abstract/Summary:PDF Full Text Request
Convolutional Neural Networks(CNN),as one of the most important algorithms of Deep Learning(DL),adopts a weight-sharing network structure to reduce the complexity of the network and is widely used in computer vision and other fields.Traditional convolutional neural networks are implemented based on central processing unit(CPU)or graphics processing unit(GPU).At present,the calculation speed of using the CPU to execute the convolutional neural network is relatively inefficient,and it is difficult to meet the real-time computing requirements;and the high power consumption characteristics of the GPU make it unsuitable for the application on a mobile platform.Field Programmable Gate Array(FPGA)owning rich computing resources can support highly parallel computing,can effectively support the calculation of convolutional neural networks.Aiming at the parallel computing characteristics of convolutional neural networks and starting from the cost of hardware implementation,an efficient FPGA-based convolutional neural network accelerator is designed.The accelerator is realized by a software and hardware cooperative computing platform,in which the hardware part realizes the acceleration of the network by unfolding convolution calculation,and the software part realizes the control and display of image data.On this basis,a system accelerator architecture based on multiple FPGAs is proposed.The calculation tasks are dispersed to multiple FPGAs interconnected through high-speed interfaces,and this architecture further improves the efficiency of the system compared with a single FPGA architecture.The hardware accelerator designed and implemented has achieved the same recognition rate as the existing work on the classification of the CIFAR-10 data set.In terms of computing performance,the single FPGA-based accelerator reached 17.9 GOPS(billion calculations per second),and the multi-FPGA co-accelerator reached 58.3 GOPS.Compared with CPU-based software recognition,it has a great improvement.
Keywords/Search Tags:Convolutional Neural Networks, Hardware Accelerating, Field Programmable Gate Array, Parallel Computing
PDF Full Text Request
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