Research On Convolutional Neural Networks Accelerator Based On FPGA

Convolutional neural networks are widely used in image recognition,speech recognition,face recognition and semantic analysis.The network structure is complex,and there are many hidden layers which contain a large number of multiply and accumulate operations,so it is a computationally intensive and resource intensive network.FPGA has lower power consumption than GPU and is more flexible than ASIC.It's a kind of hardware platform for accelerated calculation that combines performance and power consumption.Aiming at the problem of long calculation time and high power consumption in convolutional neural networks,this paper studied the accelerated calculation of convolutional neural networks based on FPGA platform.Firstly,through the research on the forward calculation and back propagation process of convolutional neural networks,the convolutional neural network's convolutional layer,sampling layer and fully connected layer are analyzed.Then the parallelism in the forward computation process is studied,including the internal parallelism of the convolution window,the parallelism between convolutional windows on the same feature map and the parallelism between convolutional windows on different feature maps.The similarity of the computational structure of convolutional layer,sampling layer and fully connected layer is analyzed.A method transforming the calculation of fully connected layer and the calculation of average sampling into convolutional layer is proposed.A general computing unit including convolution calculation module and sampling calculation module is designed.Each layer of the network reuses this general computing unit to complete the calculation of the entire network.The architecture of the accelerator studied in this paper is the host + controller + FPGA general computing unit,which accelerates the forward calculation process of the convolutional neural network.The host sends the picture to the controller,and the controller calls the general computing unit to calculate and return the result.The dataset used in the experiment is CIFAR-10,and the same network structure is calculated on the CPU and FPGA platform respectively.The comparison results show that the FPGA parallel acceleration calculation is faster than the CPU and the power consumption is lower than the CPU under the same network structure.