Design And Implement Of FlexE Mux/Demux In Aware Mode

With the development of Ethernet,it has become one of the basic carring network of mobile network.However,with the advent of 5G era,people put forward higher requirements for 5G carring network,including more flexible resource dynamic allocation,lower delay,larger bandwidth and more differentiated bearer.And the traditional Ethernet technology has been difficult to meet the above requirements,so Flexible Ethernet came into being.On the basis of traditional Ethernet,Flexible Ethernet introduces a new FlexE shim layer to decouple MAC and PHY,so as to realize the flexible adaptation of the two rates.Firstly,based on FlexE protocol,the FlexE shim layer structure and FlexE working mode are introduced in detail.Combined with G.709 protocol,it puts forward the overall design scheme for the mux and demux part of FlexE in aware mode.For the key functions of mux and demux,the read-write operation based on RAM array is adopted.At the same time,a new slot allocation algorithm is used to optimize the design of read-write control part of RAM array.The algorithm mainly includes "slot separation" and "bucket shift".Compared with the traditional slot allocation algorithm,the new slot allocation algorithm simplifies the control logic of read-write operation and greatly saves RAM array resources.Secondly,a hardware configuration method is designed for the read-write rule configuration of the new slot allocation algorithm,which can reduce the consumption of hardware resources as much as possible and avoid the disadvantage of slow software configuration.Finally,in order to meet the requirement of G.709 protocol for continuous arrangement of overhead blocks in FlexE partial rate group,the FlexE instance data stream is preprocessed before mux operation,and the corresponding recovery operation is performed after demux to recover the original FlexE instance data stream.After building the software simulation environment,the key modules in the overall design are simulated,and the functional correctness of each module is verified by analyzing the simulation results.The overall function of the circuit is verified by FPGA test,which proves that the circuit can correctly realize the mux and demux operation of FlexE instance data stream.And the maximum working frequency is 326.05 MHz.It shows that the design of this paper has reached the design goal,which can be used as a reference for the related design.