Design Of 40Gb/S 1:4 Demux

With the rapid development of Internet and wide application of information technology, the serial communication interface SerDes is becoming the mainstream of high-speed interface technology. As the main module of SerDes receiving system, the high-speed serial signal is converted to the low-speed parallel signal under the control of the clock, so that the data can be output correctly. The phase jitter and the logic correctness of the data directly affect the reliability of the receiving system. With low power consumption, low jitter and to design easily, the tree structure has become the first choice for the design of demux.In this paper, the 40Gbps 1:4 demux applies TSMC 65nm LP CMOS technology.Under the control of the 20GHz clock, the 40Gbps high-speed serial signal is converted to 4 low-speed parallel signals with the speed of lOGbps.In this paper, the structure of the 1:4 40Gbps demux and the design of the latch are improved, and then further reduce the power consumption of the system. The traditional 1:4 demux is generally two tree branch demux structure with the basic unit of the 1:2 demux,but in this paper, the 40Gbps 1:4 demux uses a multi phase clock structure, reduces a 1:2 demux, and increases two latch to retiming, and thus greatly reduces the power consumption of the system. Latch is the basic component of the demux.The high-speed latch adopts the non tail current mode latch(CML),and the low speed latch uses dynamic load non tail current mode latch(CML), which completes the conversion of CML level to CMOS level.At last,the CMOS dynamic latch is used to retiming data to synchronize four output data.Three kinds of latch are used in different structure, which greatly reduces the system power consumption, and which is the main innovation of this design.The post-simulation results show that the 40Gbps 1:4 demux in this paper is able to work regularly under all process corners.When the input signal is 40Gbps data and 20GHz clock, and under tt process corner, the total power consumption of the demux is 13mA from 1.2V supply (including buffer).The system output four lOGbps parallel data, the logic is correct, and the eye diagram is clear.The DEMUX occupies a chip layout area of 0.52mmx0.53mm.