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Research And Implementation Of Object Detection Acceleration Method Based On FPGA

Posted on:2022-10-13Degree:MasterType:Thesis
Country:ChinaCandidate:G ZhangFull Text:PDF
GTID:2518306560955619Subject:Electronics and Communications Engineering
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Convolutional neural networks have been widely used in the field of computer vision,especially the object detection methods based on convolutional neural networks have received widespread attention in both academia and industry.However,due to the high computational complexity of convolutional neural networks,current object detection methods usually rely on large servers such as GPU(Graphics Processing Unit)for operations.However,the current GPU platform has shortcomings such as high power consumption,large size,and high cost,making it difficult to apply object detection methods based on convolutional neural networks to lightweight platforms such as mobile robots and unmanned aerial vehicles.Aiming at the light-weight and fast object detection problems and requirements,this paper takes the classic YOLOv2 object detection method based on convolutional neural network as an example.Based on the FPGA platform,a software and hardware cooperative,resource-energy-aware object detection is designed.The algorithm accelerates the system hardware platform,and the convolutional neural network hardware acceleration method is studied,and the acceleration research of the object detection algorithm based on FPGA is realized.The main content of the article is as follows:First,for the design of a high-performance object detection acceleration system hardware platform,this paper develops a resource-energy-aware FPGA accelerator based on the CPU+FPGA heterogeneous architecture.On the CPU side,the image preprocessing and image post-processing modules of the object detection system based on the FPGA platform are designed to perform related transformation operations on the input and output images respectively to make them meet the requirements of accelerator input and detection.On the FPGA side,a convolutional layer acceleration method based on parallel block execution and a parameter quantization acceleration method based on dynamic fixed-point quantization are proposed to ensure the operation speed of the object detection and the low-power operation of the system platform.Through the above research,the design of the hardware platform of the object detection algorithm with high energy efficiency and high performance density is realized.Secondly,in order to effectively improve the calculation speed of the object detection algorithm,this paper studies the hardware acceleration method of the convolutional neural network.On the one hand,a dynamic fixed-point data quantization method is designed.By quantizing the parameters of the convolutional layer with 16-bit fixedpoint data,the complexity of the parameters and the amount of off-chip storage are reduced,and the calculation speed of the system is guaranteed.On the other hand,a block parallel convolution algorithm is proposed.By designing a loop expansion method,the two-dimensional expansion of the number of output and input feature maps is realized,which improves the execution parallelism of the convolution operation and realizes the system acceleration;and study a circular tiling method,which realizes the block multiplexing of on-chip resources,reduces the number of transmissions of offchip data and on-chip data,thereby reducing the delay of system operation,and improving the CNN-based computational speed of the object detection algorithm of the neural network.Finally,in order to verify the performance of the accelerator system platform,this paper carries out related experiments from the energy-efficiency,performance-density and object detection performance of the accelerator system.The experimental results show that the FPGA-based YOLOv2 object detection hardware acceleration system platform realizes the lightweight energy resource-friendly acceleration of the object detection,which verifies that the FPGA accelerator system platform designed has good performance.
Keywords/Search Tags:Object detection, Field Programmable Gate Array, Hardware acceleration, Convolution optimization, Dynamic fixed-point data quantization
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