Research Of Hardware Acceleration Technique For Image Matching Applications

Image matching technology in military and civilian fields will have a very high value, which involves a variety of image processing algorithms, and its processing speed also is one of a challenging problem. Therefore, the research of hardware acceleration technique for image matching applications is very important for real time image processing.In this thesis, we analysis a variety of filtering, edge detection, binarization and distance transform algorithms, and accelerate some of them on FPGA. With the algorithm's inherent parallelism and quantity of data, we show a accelerating structure for sliding window algorithm, use a hierarchical storage structure, design a more scientific storage control strategy, and dig data reutilization declining demands in communication and memory resources. Using data reutilization and all kinds of parallel processing technology, we improve the system capability highly and satisfy the requirement of real time ability.By defining new statistic, variance between clusters is replaced by statistic comparing, and float-point computation is transited to more precision fixed-point computation, So a pure precision threshold selection is implemented. This method provide improvement of frequency and complex computation avoidance.Finally, we make the accelerated image processing algorithm connected together, using pipelining and parallel processing technology, to create an image matching system. The system has a very accurate matching results compared with the result of PC's, but has a higher speedup.