Research On Efficient Adaptive Routing Technology For Networks-on-Chip

With the increase of the number of cores on multi-core chips,the design of an efficient on-chip interconnection network becomes very important.Endpoint congestion is one of the most challenging issues when designing low latency and high bandwidth on-chip interconnection networks.Tree saturation caused by endpoint congestion seriously decreases network performance.Adaptive routing algorithms utilize dynamic network states to route packets around congestion areas and mitigate network congestion,but cannot deal with endpoint congestion.Existing adaptive routing algorithms mainly take the current route information into account,and rarely use the route information of past packets.In this paper,we utilize the past route information to improve VC selection strategy.We conduct extensive simulation experiments to compare different algorithms.The evaluation results show that our design alleviates the impact of tree saturation and achieve higher throughput on both synthetic and trace-driven workloads.Adaptive routing is an evolving research area,due to its excellent features,such as load balancing and fault tolerance.However,out-of-order packets can be introduced due to the feature of multi-path transmission of adaptive routing.Thus packets need to be reordered at the destination before being absorbed,which requires a large buffer to reorder the packets and this can exceed design space.Therefore,the challenge is to balance the trade-off between multi-path transmission and packet reordering.In this paper,we propose a novel packet reordering metric to quantify the degree of out-of-order.To minimize the degree,we propose an orderaware network-on-chip router.First,we performs in-buffer reordering by reordering packets queuing in the input buffer.Second,packets from different input ports are reordered.We evaluate our design and the results show that the degree can be decreased dramatically with comparable performance to the baseline.