Research Of The Efficient Communication Method With Congestion-aware In Network-on-Chip

As a new kind of on-chip interconnection architecture, the main advantages of Network-on-chip lie in strong extensibility, low delay and high bandwidth.However, failures in a router or a link between routers will cause network performance loss, leading to local congestion.In addition, with the number of cores in a single chip becoming larger and larger, network-on-chip cannot solve the problem of long interconnect in the plane gradually. By stacking layers with TSVs, three dimension Network-on-chip can solve the above problems.To overcome restrictions of the manufacturing technology and improve utilization of TSV resources, partionally vertical interconnection architecture in three dimension emerges.In this paper, deep study of the network-on-chip conducts. The aim of the study is to make full use of TSV resources, improve the efficiency of network communication and to balance network traffic. Main works of this paper are as follows(1) This paper puts forward a fault-tolerant routing algorithm, aiming at a path fault and local congestion in Network-on-chip. Firstly, the algorithm designs a fault model that reflects the fault status of the path within two hops. As a result, this novel fault model makes the router achieve a dynamic perception of path state within two hops with less cost. Secondly, a novel congestion model has been proposed for reflecting the state of the local network more accurately, contributing to balance network traffic. Finally, when a fault occurs, the algorithm is not only fault-tolerant but also makes sure the network a good performance. What’s more, the algorithm chooses the optimal path under the condition of fault-free. Experimental results show that the proposed algorithm has higher throughput rate and lower latency than contrast cases when the network is fault-free. In the case of defective in the network, the advantage of the present scheme has a bigger superiority.(2) The paper proposes an efficient method of reconfigurable TSV with reuse arbiter called RTwRA. The proposed method aims at improving TSV resource utilization of partionally vertical interconnection architecture in the three dimensions. First of all, SVCs are added in nodes for nterlayer communication; secondly, TSV channel reconfiguration is proposed. Once meeting the relevant conditions, configure available TSV channel into a bidirectional channel and complete efficient transmission between layers; at last, design a reusable arbitrator, realizing the arbitration priority of related data in the SVC. Comprehensive the above designs, the proposed method can relieve TSV congestion situation. At the same time, the method can improve the resource utilization of TSV. Compared to the reference objects, the experimental results show that the proposed scheme has certain advantages of network performance.