Design LNA And PA Circuits Of A Sub-1GHz RF Transceiver Chip For TPMs Application

Among wireless communication technologies,Lo Ra technology has been continuously expanding to obtain many new applications with its low power consumption,long communication distance and other characteristics.The radio frequency front-end circuit is one of the important parts of the wireless communication system,and it also determines most of the power consumption of the system.Therefore,it is the research goal of this dissertation to make the trade-off between the expected performance index,chip size and cost of the radio frequency circuit to achieve the best comprehensive design.The RF front-end circuit designed in this paper is applied to the tire pressure monitoring system.The core module low-noise amplifier,power amplifier and matching network are researched and designed,and the circuit and layout design based on 110nm CMOS process and post-simulation verification are carried out.The main research results of this paper are as follows:(1)A low-noise amplifier(LNA)without on-chip inductance which using current multiplexing technology is designed.The amplifying structure of the circuit adopts NMOS and PMOS in series,and the equivalent resistance value of the PMOS body resistance is used as the load.The circuit does not require the inductive and capacitive load in the traditional structure.The final layout area of the LNA part is0.387mm*0.199mm,which saves about 50%of the area compared with other designs that achieve the same performance.The simulation results of the final circuit show that,within the operating frequency range,the LNA gain is greater than 23.5d B,the maximum is 26.5d B,the reflection coefficient S₁₁is less than-10d Bm,and the noise figure is basically maintained at 2.23d B.At 433MHz frequency,P_{1d B}of the circuit is-12.35d Bm,and IIP3 is-4.825d Bm.Under the voltage of 1.5V,the power consumption of the circuit is 4.2m A.(2)A class E power amplifier(PA)is proposed.In order to achieve different output power at different distances,the power amplifier uses 8 groups of parallel transistors,and the 3-8 decoder controls whether it is connected to the circuit.The layout area of the power amplifier is 0.323mm*0.09mm.The simulation results of the circuit show that in the operating frequency range,the output power of the circuit is greater than 14.62d Bm,the maximum is 17.4d Bm at 433MHz,and the maximum PAE is 53%.The power consumption of the circuit is 50m A.(3)Integrate the designed LNA and PA and add pins to form an overall layout.The two circuits are connected to the antenna through the same port.Consider that the signal reception of the LNA will be affected by the capacitance and inductance of the PA terminal.Under the premise,the matching network which is selected in the design gives up 20%of the PA end performance to ensure the performance of the LNA.In summary,this paper analyzes and optimizes the circuit design of the key module low noise amplifier,power amplifier and its matching network of the RF transceiver.The post-simulation verification results show that the chip performance meets the design requirements and will be put into tapeout.