The Design Of A High-speed 12bit 200MS/s Pipelined-SAR ADC

With the continuous development of wireless network communication links,the signal receiving end of the communication link has higher and higher requirements on the performance indexes of analog to digital converters.Pipeline ADC has a high sampling rate,but it consumes a lot of power and is not compatible with advanced technology.Successive Approximation Register ADC has the advantages of low power consumption.But its capacitance matching accuracy limits its resolution.Pipeline successive approximation analog-to-digital converter(Pipeline SAR ADC)breaks through the bottleneck of SAR ADC in accuracy and sampling rate,and also has good power efficiency,which is suitable for modern communication systems,so it has gradually become a research hotspot.Meeting the application of high-speed communication systems,the thesis designed a two-stage Pipeline SAR ADC with a resolution of 12 bits and a sampling rate of 200 MS/s.The paper establishes a two-stage Pipeline SAR ADC model based on pseudo-differential ring amplifier,analyzes the impact of non-ideal factors on ADC performance,and designs the corresponding circuit.Among them,the capacitor array of first-stage SAR ADC is divided into two arrays,one for high-speed successive approximation operation,and the other for generating low-noise residual voltage,which accelerates the conversion speed of the first stage;Improved and designed the pseudo-differential loop amplifier with"double self-zero"reset,and makes its linearity improved,and use it as a residual amplifier in the Pipeline SAR ADC;combined with"half-reference"technology to solve the problem of gain error caused by insufficient open loop gain of the pseudo-differential ring amplifier.The second-stage SAR ADC uses an asynchronous SAR logic architecture.In the capacitor array design,the size of the dummy capacitor is increased,which not only reduces the reference voltage of the second stage,but also increases the load capacitance of the ring amplifier,thereby improving its loop stability.The presented SAR ADC is implemented in TSMC 40nm CMOS process,the core area of ADC is0.042mm~2,Post-simulation shows the ADC exhibits 11.49 bit ENOB,83.72d B SFDR and 4.3m W power consumption at a Nyquist input frequency when operating at a sampling rate of 200 MS/s and 1.1V power supply.FOM is 7.47f J/conv.step,and meet the design requirements.