| Analog-to-digital converters (ADC) are key design components in digital communication and signal processing systems as they provide the link between the analog world and digital systems. There are many ADC architectures available, each with different advantages and disadvantages. The pipelined ADC is used in this thesis as it possesses a good balance of speed, resolution, and power dissipation. This thesis will put forward two different pipelined ADC designs. One design will be switched capacitor and the other will be switched current. Switched capacitor designs process signals as voltages and store the information as charges on linear capacitors as the switches open and close. Switched current designs, on the other hand, process the signals as currents and store the information on the MOS transistor gate capacitors. The switched capacitor design has a speed of 50MS/s, 6 bit output, SINAD of 36.54 dB, INL of 0.8 LSB, DNL of 0.6 LSB, power of 34mW, and voltage supply of 1.8 volts. The non-boosted switched current design has a speed of 50MS/s, 6 bit output, SINAD of 35.64 dB, INL of 0.62 LSB, DNL of 0.81 LSB, power of 45mW, and voltage supply of 1.8 volts. The boosted switched current design has a speed of 60MS/s, 6 bit output, SINAD of 35.43 dB, INL of 0.74 LSB, DNL of 0.85 LSB, power of 45mW, and voltage supply of 1.8 volts. This thesis uses the 0.18um generic CMOS process from the Cadence design kit. |
