Design And Implementation Of High-performance Signal Processing System Based On Arria10 FPGA

With the increasing demand for the processing power and transmission bandwidth,high-integration and low-power have become the main trend of the next generation of high-performance processing platforms.In the field of radar signal processing,since FPGAs have better power consumption than most processors,the architecture of high-performance signal processing systems based on FPGAs is of great significance for improving overall processing performance and processing power per unit volume and power consumption.In actual system design,multi-chip processors are often implemented in a highly integrated form to increase the processing density.However,there are two key technologies needed to solve in the high-density processing systems.This paper proposes the optimized solutions for these two key difficulties.The details are as follows:First of all,in the design of high-speed DDR4,this paper proposes an S-parameter model to quantify the relationship among the winding delay,the serpentine line height,the line spacing and the signal frequency.The results show that within a certain threshold,the serpentine winding delay is related to the serpentine line height,the line spacing and the signal frequency.It shows a certain functional relationship.After a certain threshold,there is little relationship with the three.This conclusion can effectively solve the problems of synchronization.In addition,the conventional daisy-chain topology is analyzed and optimized.A new type of three-dimensional daisy-chain topology considering PCB as a three-dimensional space structure is proposed.Modeling and simulation verified that the new three-dimensional daisy-chain topology can effectively reduce the non-ideal effects of multi-loaded branch lines and vias,greatly increasing the noise margin at the receiving end,and providing the chip interconnection design.Secondly,in the optimization of power distribution network(Power Distribution Network,PDN),paper build a common capacitor library model,and propose a low-high-low-band PDN optimization method based on the frequency domain target impedance method.The idea is used to complete the simplification and optimization of the PDN.It reduces the design difficulty and cost.Finally,a set of high-performance processing platforms based on Arria-10 FPGAs was designed,and the performance of the next-generation processing platform was verified through simulation tests.The read-write speed of the cache DDR4 reached 2133 Mbps,and the measured bandwidth reached 12.75GB/s(76% of the ideal bandwidth),achieving a new generation of signal processing platform with higher-speed and higher-density.