Design Of Arithmetic Circuit Based On XOR And Majority Gate Using Quantum-dot Cellular Automata

As the feature size of CMOS(Complementary Metal Oxide Semiconductor)continues to shrink,the integrated circuit industry will face more challenges.QCA(Quantum-Dot Cellular Automata),as one of the various nano-devices,has the characteristics of high integration,low latency,and low energy dissipation,and it is one of the most likely candidates to replace CMOS devices.The basics of QCA are majority gates and inverters.However,some studies have found that the addition of XOR(Exclusive-OR)gate can make the expression more compact.XOR gates often play an important role in arithmetic circuits.In this thesis,two different types of circuits are designed by optimizing the expression of the decimal full adder.One is a decimal full adder based on RCA(Ripple Carry Adder),and the other is a decimal adder based on parallel BCD(Binary Coded Decimal)full adder.Then according to the design requirements of logic synthesis,a three-input XOR gate based on majority gates was designed.The main content of the thesis is as follows:1.After analyzing the XMG(XOR-Majority Graph),we optimize and rewrite the expression of RCA decimal full adder,and then draw a new QCA circuit based on the expression.The results have been greatly improved compared with the original design,in which the 1-digit decimal full adder reduced by 52.6% in area and the delay was reduced by 25%.2.According to the theory of XMG,we logically rewrite the decimal full adder based on parallel BCD decimal full adder.Combined with the optimization measures and the excellent carry propagation method of this design,the 8-bit decimal full adder designed in this thesis has an improvement that area was reduced by 55.4%,and latency was reduced by 34.5%.3.The mainstream logic synthesis tools are designed based on logic nodes.Therefore,we propose a three-input XOR gate based on majority gates and apply it to parity checker.Compared with previous parity checker which is based on majority gates,the area and delay of our proposed XOR gate are reduced by 17.2% and 17.3% on average.