A Analysis And Designs Of XNOR Gate For Quantum-dot Cellular Automata

Since the first transistor in the world came out,the electronic technology industry began.With the large-scale development of integrated circuits,integrated circuit technology with CMOS devices as the core has emerged.Since then,the integrated circuit industry has developed rapidly,and Moore's Law has developed.It has also been predicting the development of the integrated circuit industry.According to Moore's Law,the number of IC-capable devices doubles every 18 to 20 months.With the continuous advancement of the integrated chip manufacturing process,the degree of integration of the circuit is also increasing,which makes the size of the integrated circuit smaller and smaller.The shrinking of the size of integrated circuits will lead to a fundamental change in the physical properties of the devices themselves.High power consumption,high density,and signal crosstalk are all obstacles to the development of integrated circuits.Therefore,the research and development of new devices that can replace CMOS has always been the long-cherished wish of scientific researchers.Thus,nanodevices have been developed,and in many nanodevices,Quantum-dot Cellular Automata(QCA)proposed in 1993 is one of many alternatives to CMOS devices.QCA has been extensively studied with a completely new computing model and special conversion binary information.The key to QCA circuit research lies in stability and power consumption.This article focuses on the analysis and design of QCA circuits.In the aspect of presenting the same or gate logic circuit,the probabilistic transfer matrix is used to estimate the stability of the circuit,and the energy dissipation of the XNOR gate circuit is analyzed in the QCAspecific power analysis software,so that the XNOR gate is accurately analyzed and evaluated.To realize the feasibility of combinational circuits,combined with the design rules of QCA circuits and the special structure of the QCA XNOR gate itself,a digital comparator is implemented using a three-input XNOR gate,although the area and delay advantages are not obvious but are complex.Compared with the predecessor,the optimized one-byte value comparator was optimized for 22.2%,and the optimal threebyte optimization was 40.18%.A ripple carry adder and a parity checker were designed with a five-input XNOR gate.The ripple carry adder circuit has a simple structure and is easy to expand.The four-bit parity checker is more than the previous ones.Although the advantage of area and complexity is not obvious,the delay is reduced by 28.6%.Therefore,the idea of implementing a parity checker based on a five-input XNOR gate is feasible.