FPGA Design Of Multi-channel Broadband AD Acquisition

With the development of modern communication and radar technology,the working bandwidth of the system continues to increase,which requires high-speed sampling of the front-end acquisition system to implement the digitization of broadband signals.In addition,the high-speed ADC index is also rising,which brings the possibility of broadband acquisition,so it is of great significance to design a broadband acquisition system based on high-speed ADC.In this paper,a high-speed ADC is used to perform direct band-pass sampling of the broadband signal,and at the same time pre-process the sampled signal to implement a broadband acquisition and signal pre-processing subsystem.First,the three sampling structures based on Nyquist sampling theorem are introduced and analyzed,and the sampling architecture of RF sampling is determined.According to the design requirements,the implementation architecture of AD + FPGA is used,and the basis for device selection is given according to the requirements.The high-speed ADC is selected AD9680,and the cost-effective FPGA is selected from XILINX XC7K410T.The communication between AD9680 and FPGA adopts JESD204B protocol.In this design,the communication between AD9680 and FPGA adopts the subclass 1 mode of JESD204B protocol,and implements the logic design of the interface protocol on FPGA,and implenments the multi-channel synchronous acquisition.The down-sampled data after the 204B deframe needs to be sent to the host computer for processing to analyze the performance of the ADC.Here,the data transmission with the host computer is completed through the Gigabit network.On the MATLAB,the ADC's SNR,SFDR and The scope and channel isolation are analyzed,the theoretical basis and test methods of these three indicators are given,and finally the performance of the ADC is evaluated based on multiple indicators.The communication between the AD acquisition board and other boards is transmitted through optical fiber,and the user layer logic design based on GTX optical fiber communication is introduced.Finally,the article discusses multi-channel signal preprocessing,introduces the principle of digital down conversion,and gives the FPGA logic design of the algorithm.In addition,the digital pulse compression of the infinite data sequence with high data rate is studied,and the required resources and operation efficiency of the four FFT architectures of the FFT IP core,pipeline architecture,base two burst architecture,base four burst architecture,etc.are analyzed.The implementation method of pulse compression is segmented and compared with MATLAB simulation results to verify the rationality of the design.