The SOPC Implementation Of I-CASH Page Compression Subsystem

SSD (Solid State Disk) storage technology has been developed very quickly recent years, and has some storage market occupancy due to its high performance. However, there is still a great gap between the life span and cost of SSD and those of HDD (Hardware Disk Drive). Therefore, hybrid storage technology which combines both SSD and HDD technology and take advantage of each characteristic appears. By using hybrid storage technology, we can achieve high performance which is close to SSD and long life span and big capacity which are close to HDD.I-CASH (Intelligently Coupled Array of SSD and HDD) is a special parallel structure hybrid storage. I-CASH takes advantage of content locality. It stores reference page data which is not frequently changed in SSD and store the delta data which is frequently changed in HDD. so it can achieve several times performance of HDD. Otherwise, I-CASH reduces write operation in SSD, so the life span of SSD can be extended.This paper introduces the structure of I-CASH, the SOC main control chip implementation. In this implementation, main data computing is operated by specific integrated circuit in chip. Due to the complexity of the whole I-CASH system, this paper only presents the research about the design of I-CASH page compression subsystem and the implementation in FPGA. The structure of compression subsystem and implementation of each module is introduced, especially the core data computing module is introduced in detail. The data compression algorithm and data format stored in HDD is introduced.The design has been validated in FPGA, this I-CASH page compression subsystem can complete page data compression and decompression correctly. By changing different reference page data and writing data, tests under different situation have been done. The speed of operation in data compression and decompression is about150MB/s.