Simulation of FinFET Electrical Performance Dependence on Fin Shape and TSV and Back-Gate Noise Coupling in 3-D Integrated Circuits

The constant push to achieve greater circuit density has finally reached the physical limits of planar technology. Emerging and future solutions rely on three-dimensional (3-D) semiconductor architectures for transistors (multi-gate devices including FinFETs) and for integrated circuits (3-D ICs). These novel technologies present many new challenges this thesis addresses including transistor design optimization for FinFETs and noise coupling analysis for 3-D stacked ICs.;FinFETs have emerged as the solution to short channel effects at the 22 nm technology node and beyond. Previously, there have been few studies on the impact of fin cross-section shape on transistor leakage. This thesis shows for the first time that fin shape significantly impacts transistor leakage in bulk tri-gate nFinFETs with thin fins when the fin body doping profile is optimized to minimize leakage. It also shows how fin shape can be used to implement multi-threshold nFinFETs without modifying transistor footprint or increasing area consumption.;The capability of stacking dies from various technologies within a 3-D structure will eventually allow for FinFET integration. Within 3-D ICs, through-silicon vias (TSVs) are a known source of substrate noise in planar bulk technologies. While FinFETs are expected to demonstrate superior noise immunity relative to planar devices due to superior gate control over and volume inversion of the active fin, the impact of TSV noise on FinFETs has not been previously quantified. To evaluate TSV-FinFET noise coupling, this thesis develops a simulation methodology that extends the state-of-the-art by accurately modeling noise from digital signals on nearby TSVs and improving the accuracy of full-wave electromagnetic extraction of noise propagation through the bulk substrate.;3-D integration introduces unique noise sources not present in planar ICs. This thesis identifies a new noise source specific to 3-D Fully Depleted Silicon on Insulator (FDSOI) ICs---the parasitic back-gate effect due to interconnect patterned on the backside of FDSOI transistors. A framework is developed to evaluate the impact of process parameters. Results show that coupling due to backside metal results in 5X more electrostatic noise coupling than nearby through-oxide vias (TOVs).