Improving the performance of a DSP microprocessor architecture

An exploration of a microprocessor architecture for Digital Signal Processing is presented. The exploration methodology is similar to the analyses used in the design of Reduced Instruction Set Computers.;The proposed architecture is shown to improve the performance by a factor in the range of 1.25 to 2.11 across the benchmarks on a per clock basis.;An implementation proposal for the architecture is presented that enumerates the additional resources required by the proposed architecture and includes floorplans for a VLSI implementation.;The proposed architecture is compatible with the Motorola DSP56000 microprocessor at the assembly code level, but employs greater pipelining to improve performance. High-level simulation of the 56000 and the intermediate experimental architectures is used to characterize the execution of a suite of benchmark programs. The profiling data is used to reorganize the architecture to improve performance.