Research On The Performance Prediction Model For CMT Architecture

With the rapid development of multi-core processors and the performance of the processor,the power density of the processor chip is also rising rapid.The problem of power wall becomes more and more serious and concern.And it has become a bottleneck to further enhance the performance of the processor.How to improve th energy of the system is a very important issue.Accurately,performance prediction estimation model can provide a significant basis for energy consumption optimization and operating system scheduling.The performance estimation model constructed by this paper is complied using performance counter to sampling the run-time information of the system(such as branch prediction failure rate,L1 Cache hit rate).In this paper,a performance prediction model(SCP)is constructed for CMT architecture,which can provide reference information for power regulation.CMT artitecture is a multi-thread structure,which first appeared in the AMD Bulldozer processor.Due to the multithreading nature of the CMT architure,power and performance can be banlanced by the “thread migration and PG”technique,and it is important to be able to accurately and quantitatively predict the post-conditioning performance prior to conditioning.With analysis,we find that the performance of thread migration in CMT architecture has a great relationship with the use of shared resources,like L1 instruction cache,floating point computation unit,L2 Cache and so on.The use of shared resources through the processor to provide hardware performance counters can be monitored.According to the above information,this paper constructs the SCP model by performance counter and linear regression method,and carries out experiment on AMD FX-8320 experimental platform.The model can predict the performance of a thread running in the aggregate state(isolated state)according to the running information of the thread in the separated state(aggregation state).At last,the error of the model is about 6% by testing the assembly.At the same time,in order to further validate the validity and applicability of the model,a performance power consumption prediction model PPEP-SCP is proposed by combining the power consumption prediction model PPEP of DVFS regulation technology with the SCP model proposed in this paper.The model combines the characteristics of the two sub-models to predict both performance and power consumption across both the VF level(voltage and frequency)and the operating states of the threads(aggregated and separated states).At the same time,we propose the application strategy for the PPEP-PPCP model and the PPEP-SCP model respectively,and compare the experimental data.As the fusion model can balance power consumption and performance through two kinds of adjustment methods(DVFS and thread migration + PG),it is closer to the target power consumption and achieves higher performance than the PPEP model in the Power Capping scenario.