Atlas: A dynamically parallelizing chip-multiprocessor for gigascale integration

The single-chip multiprocessor is an important direction for future microprocessors. This architectural approach reduces the number of long interconnects, reduces design time, and improves performance for many applications. The stigma of a single-chip multiprocessor is that many important applications cannot be automatically parallelized and that performance suffers with "dusty-deck" binaries. This thesis explores the architecture of a single-chip multiprocessor that engages a combination of aggressive speculation techniques to enable the dynamic parallelization of irregular, sequential binaries. The thesis then examines future technologies to substantiate the assumption that increasing wire delay favors multiprocessor solutions. Contributions to the field of computer architecture include: (1) The microarchitecture of a chip-multiprocessor enhanced for thread speculation and data value prediction is described and evaluated (Chapter 2). (2) The thesis explores methods to dynamically partition a sequential program into threads. A new dynamic partitioning strategy is developed and shown superior to current approaches (Chapters 3 and 4). (3) An improved data value predictor is developed by applying ideas from branch prediction research to data value prediction. A new correlated value predictor is defined and evaluated (Chapter 5). (4) A quantitative exploration of architectural alternatives for 100nm technology is performed. Results show that a system composed of a small number of moderately complex processors provides the best performance over a wide range of applications. (5) The relationship between key technology parameters (inter-cluster wire delay and transistor switching delay) and key architecture parameters (superscalar vs multithreaded instruction dispatch, and value prediction support) is investigated for clustered microarchitectures. It is demonstrated that multiprocessor designs are substantially more tolerant to increasing wire delay than uni-processor designs. (6) The framework for a new analytical IPC model for microprocessors is developed and compared against an existing approach.