| This thesis focuses on the characterization of the operation, as well as on the hot-carrier effects in Flash memory devices.; High electric fields in the tunnel oxide, necessary for program and erase operations of the Flash memory cell, cause tunnel oxide degradation through generation of both interface traps and oxide charge. This degradation is identified as the main source of Flash memory reliability concerns. In order to gain a better understanding of these reliability concerns, an improved oxide-charge and interface-trap lateral profiling charge pumping technique (iLPCP) is proposed. Erase-induced oxide charge and interface traps are investigated in Flash memory devices. It is shown that the improved technique allows the extraction of profiles in cases where the previous method does not yield satisfactory results. To elucidate the advantages and the limitations of the improved technique, a comparative study of iLPCP and of an existing direct current (DCIV) technique for lateral profiling of interface traps is conducted: both erase- and program-induced interface traps are investigated in Flash memory devices. The results indicate that (1) iLPCP probes a much bigger portion of the gate region, (2) iLPCP probes a wider energy range, but (3) DCN is more sensitive deep in the channel and thus complements iLPCP.; It is well known that in recent years, as a consequence of the hot-carrier-generated reliability concerns, the Flash memory tunnel oxide scaling has essentially stopped at about 90–100 Å. This particular scaling is a major technological challenge, since it would allow for faster operation, lower operation voltages, and more efficient chip design. As a potential solution to this problem, in this work we demonstrate for the first time a Flash memory cell with scaled-down 55Å EOT JVD silicon nitride tunnel dielectric. The operation of the novel Flash memory cell, programmed by two different mechanisms—CHE injection and PASHEI, and erased by CHH injection, is characterized. It is shown that the novel cell has good endurance and retention characteristics, and high program/erase speed. The use of CHH Erase operation allows full bit alterability in Flash memory, like in EEPROM, without any changes to the existing memory architecture, and eliminates the over-erase problem. PASHEI programming offers a choice of faster or low-voltage (+5 V only) operation, dependent on the intended application requirements. These results suggest that a high-quality JVD silicon nitride can be used as a long term solution to replace the tunnel oxide and to extend the scaling limit of tunnel dielectric in Flash memory devices beyond the year 2010. |
