| The introduction of turbo codes in 1993 was a major milestone in coding theory that had spurred a renaissance in iterative decoding, leading to breakthroughs in performance over maximum likelihood decoding. Since then, the works of Gallager in 1963 on low-density parity-check (LDPC) codes and Tanner in 1981 on code design from graphs have been revisited by several researchers. As a result, a new theory has emerged generalizing these ideas into codes defined on graphs and their iterative decoding via message passing.; The breakthroughs in performance recorded by turbo and LDPC codes, however, have been accompanied by an increase in implementation complexity, decoding latency, and memory overhead, posing major implementation challenges for many high-performance applications. The work presented in thesis solves these implementation challenges by developing decoder architectures optimized for high-throughput and low-power applications. For turbo codes, a new methodology is proposed for rigorously analyzing the implementation complexities of constituent decoders in turbo decoders, and for designing decoder architectures optimized for memory and latency using dataflow graphs. The methodology achieves significant improvements over state-of-the-art as demonstrated through experiments.; Decoder architectures for LDPC codes introduce another complexity dimension related to the on-chip interconnect bottleneck of LDPC decoders. A new parameterized-core-based design methodology targeted for scalable and programmable LDPC decoders is proposed. The methodology solves the problems of excessive memory overhead, high latency, and complex on-chip interconnect typical of existing decoder implementations, which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels. The methodology proposes: (1) The concept of architecture-aware LDPC code design that solves the interconnect bottleneck, (2) a faster and memory-efficient turbo-decoding algorithm for LDPC codes, and a reduced-complexity mechanism for message computations, (3) a programmable, scalable, and code-rate tunable architecture platform, and (4) a core-generator for high performance decoders. A decoder chip has been implemented using this methodology in 0.18 μm technology, which delivers a throughput of 1.6 Gbps at 125 MHz and consumes 760 mW of power. |
