Turbo Code Decoder Realization

Turbo codes have been arresting great attentions from the academia of communications and informatics since 1993 because of their excellent performance in error correction. In order to implement the turbo decoder, the iterative decoding algorithm and some technical problem in decoder implementing is discussed in this paper.Firstly, a reduced decoding algorithm is proposed based on a modified MAX-LOG-MAP decoding algorithm. In the algorithm, the forward and backward metrics calculations have been reduced and an iterative decoding procedure without estimation of SNR is proposed. The principle of choice and design of interleaver is summarized, and a high spread interleaver is selected to use in turbo decoder implementing later. Based on the MAX-LOG-MAP algorithm , a scale factor (SF) is introduced to scale the extrinsic information , then make a little modify on the decoder structure. This modified structure with scale factor is easy to implement and can improve the error correction ability of Turbo code at low SNRs.Secondly, in order to implement the decoder, some important problems are considered, such as fix-point quantification, over-flow of calculation and RAM space needed. A new way to avoid over-flow of calculation is proposed, only to calculate the difference of the forward and backward metrics and the value range of difference metrics is very small. With the reduced iterative decoding algorithm and the way to face some imortant problems mentioned above, a low complexity Turbo decoder is implemented with fix-point digital signal processor (DSP). The test result shows the performance of the decoder is close to that of float-point one.