| Field-Programmable Analog Arrays offer an ease of design, a fast turn-around time and low non-recurrent costs, but the noise inserted by the programmable circuits limits the resolution. This project implements the processing core of an FPAA using delta-sigma based digital signal processing, where the resolution is independent of the circuit noise. This digital FPAA allows the designer to trade off bandwidth for resolution, simplifies the programmable routing grid because all signals are 1-bit, and reduces the fabrication costs by using a low-cost digital CMOS process. The basic blocks of the FPAA can be programmed as a biquad filter, a sine wave oscillator or a 5-input mixer, which have a maximum SNR of 87.5dB with a bandwidth of 476kHz when operating at 244MHz. The FPAA, implemented in TSMC's 0.18μm CMOS technology, consumes 0.93W at full activity and occupies a core area of 6.28mm2. The speed of different full-adder cell architectures was also studied as part of this project. |
