Research On The Process, Device Model And Circuit Design Of A New Type Of Hafnium-based Ferroelectric Memory

Ferroelectric random access memory?FRAM?is widely considered as one of the promising,non-volatile memory candidates due to its high read-write speed,low power consumption,long retention and endurance characteristics.However,it is very difficult to further scale down the thickness of the ferroelectric thin film like Pb?Zr,Ti?O₃?PZT?,Bi₄Ti₃O₁₂?BIT?and Sr Bi₂Ta₂O₉?SBT?,which makes it almost impossible to convert ferroelectric components from low density integration to high density integration and from planar to 3D.Therefore,the research and development of novel ferroelectric memory based on new materials systems are greatly required.In this paper,the main work of the emerging Hafnium-based ferroelectric memory project is as follows.Firstly,a 9nm-thick Hf_0.5Zr_0.5O₂?HZO?ferroelectric thin film was prepared by atomic layer deposition.The HZO ferroelectric capacitor also incorporates Ti N top/bottom electrodes.The effects of annealing and mechanical clamping processes on the characteristics of ferroelectric capacitors were investigated.It concludes that the electrical properties of HZO ferroelectric capacitors,treated by annealing and mechanical clamping processes,are significantly improved.From the polarization strength voltage?Polarization-Voltage,P-V?curve,namely the hysteresis loop curve,the remnant polarization is 31?C/cm²?2Pr?with the coercive voltage about 1.6V.The study demonstrates that annealing process and deposition of Ti N top electrode process can optimize the electrical properties of HZO ferroelectric capacitors.Secondly,a macro-model of ferroelectric capacitor for circuit simulation is established and extracted from the fabricated Hf_0.5Zr_0.5O₂-based ferroelectric test structures.The macro-model is described by SPICE netlist and simulated by Hspice tools.Simulation results fit perfectly with the P-V curves from the experimental measurement results,which prove high accuracy of the established model.In addition,the single event effects?SEE?on ferroelectric HZO capacitor-based non-volatile static random access memory?nv SRAM?were investigated by simulation.The nv SRAM cell is implemented using a combination of CMOS transistors and HZO ferroelectric capacitors,namely 6-Transistors and 2-Ferroelectric Capacitors?6T2C?.An independent double exponential current source was utilized and injected into specific circuit nodes to simulate the heavy ion induced single-event transient current.The simulation results show that the transient pulse current is possible to upset the logic state of the memory cell from 1 to 0 and vice versa,but whether it can recover in a short time period after the upset errors depends on the exact value of linear energy transfer?LET?for the injected particles.In addition,changing the key parameters of the ferroelectric capacitance can mitigate the influence of single event effects.Finally,a 4K bit?512×8 bit?capacity ferroelectric memory circuit is designed based on Silterra 0.18?m CMOS technology,including the storage array,the sensitive amplifier,the row and column decoders and other peripheral circuits.The simulation results of the circuit show that the time of data writing and reading of ferroelectric memory is 20ns at 3.3V power supply.The new Hafnium-based ferroelectric memory circuit designed in this thesis lays a solid foundation for the development of high-capacity and product-oriented new ferroelectric memory in the future.