Exploration On Routing Configuration Of Heterogeneous NoC With Dynamic On-chip Resource Management

With the tremendous development of the semiconductor technology,hundreds of millions of transistors are integrated into one single chip.Nevertheless,it is difficult to increase the overall computing capability of the chip because of the Moore Limitation.The traditional chip design is based on the bus structure,and the computing core in the chip communicates through the bus.Due to the limited resources of the chip,when a large number of computing cores access the same resources at the same time,the contention of the resources is caused,which leads to a decline in chip performance and consumes a large amount of energy.Most of the currently designed chip use network on-chip technology to solve inter-core communication problems,enabling the computing core to efficiently share chip resources.The design and development of network on-chip has a significant impact on the performance and energy consumption of the chip.With the increasing complexity of computing applications in the industry,computer architecture design has gradually shifted from the traditional CPU-based homogeneous core chip to the CPU-GPU based heterogeneous core chip.The network on-chip in the era of CPU-based homogeneous core chips is not fully applicable to the CPU-GPU based heterogeneous architecture.The network on-chip design for CPUGPU heterogeneous architecture has not been studied in depth.The proposed network on-chip of heterogeneous architecture brings new challenges to the field of computer architecture.In the design of network on-chip,increasing the router buffer capacity can reduce the probability of packet loss and the probability of deflection,and improve the bandwidth utilization of the network on-chip.At the same time,the router buffer also brings a lot of dynamic power and static power to the chip,while the circuit components increase the chip area and design complexity.Due to the huge difference in CPU and GPU computing characteristic,the communication hotspots in Network-on-Chip are mostly concentrated on the communication link associated with the GPU,while the communication link associated with the CPU is relatively idle,and a large amount of buffer resources are idle.The traditional routing buffer allocation strategy makes GPU unable to get enough buffer resource,resulting in a decline in overall system performance and energy efficiency.This paper first studies the impact of different buffer allocation strategies on system communication delay and energy consumption.After comprehensive evaluation with a spectrum of benchmarks with different characteristics,this paper divides the CPU-GPU workloads into three categories according to the throughput,and combines the workloads as baseline benchmark.On the basis of the above,we reveal the implicit tradeoff between performance and energy consumption under different constrains of buffer resource.We further show that intelligently allocating more on-chip network buffer resources to compute-intensive nodes can significantly improve system performance.The experiment shows that after applying the static router buffer allocation strategy proposed in this paper,our system reduces the communication delay by 44.6%.Then,we introduce a runtime strategy that dynamically allocates network buffers to applications based on application characteristics,the resources are being used more efficiently.Our evaluation shows that our system reduces the communication delay by 55.47% on average,and reduces energy consumption of the system by 21% on average.