Error Analysis And Retuning Of The Gem5 Simulator For Android Applications

Hardware protyping a Soc chip is exceedingly expensive, that's why Soc architects rely on simulations to evaluate new ideas and designs. As a full-system simulator, Gem5 can simulate a variety of ISAs and offer a diverse set of CPU models. However, due to limitations of the Gem5's performance and accuracy, simulation errors could be ranked along with the assessment results and would impact on the designs, so it is necessary to analyze the error sources and retune Gem5.By comparing the overall performance and microarchitectural accuracy between Gem5 and Cortex A9 processor, this thesis points out the error resources and makes error corrections of Gem5. Firstly, the unextracted problem of microarchitectural performance parameters in Gem5 is resolved in this thesis, such as branch misprediction rate, L1 Cache misses and L1 Translation Lookaside Buffer(TLB)'s misses. Secondly, by running computing-intensive benchmarks and analysing the extracted performance parameters on Gem5 and Odroid U3 after making several changes to Gem5 in order to more closely match the Cortex A9 processor, the thesis finds out several micro-architecture modules, which have large impact on Gem5's simulation errors, such as branch predictor, Cache replacement policy and Cache prefetch mechanism. Thirdly, this thesis re-implements these micro-architecture modules and verifies these changes.By running Linux computing-intensive benchmarks and Asimbench, and using the Perf tool to obtain the performance parameters on Gem5 and Odroid U3 development board, this thesis compares these performance parameters and gives the average simulation error before and after error corrections:for Linux benchmark, Clock cycle Per Instruction (CPI)'s error decreases from 20.37% to 6.25%; for Asimbench, CPI's error decreases from 29.1% to 14.9%; micro-architecture performance errors are limited to 20% for Linux benchmark and Asimbench.