Design Of Video Resolution Adaptive System Based On FPGA

Nowadays,video display technology has been widely used in all aspects of production and life,but in the actual video display process,the resolution of the video source is diverse,and the resolution supported by the monitor is not uniform,so there are often cases where the resolution does not match,Resulting in the problem that the display cannot play video normally.In response to this problem,this paper adopts the design scheme of FPGA and STM32 as the core,and designs a software and hardware system for multi-channel video processing.The system is based on a bilinear interpolation algorithm and adopts pipeline design ideas.Optimize the algorithm and use ping-pong operation to cache the data;to solve the compatibility problem between the video source and the display.This article focuses on the input video resolution and divides the input video format into three types: resolution,scanning format,and frame rate.After analyzing the display scene and the power consumption of the required devices,the overall system plan is designed,and the circuit schematic and PCB are designed using Cadence software.Using a dedicated video capture chip Sil9293,the input HDMI signal is processed into a16-bit wide digital signal in YCb Cr format,and then the programmable device FPGA realizes the collection,storage,calculation,and output of the input data,and the resolution information of the input video Real-time detection.Using the high-speed parallel processing capability of FPGA,the collected 8-channel video data is alternately written into their respective RAMs,and the data storage control IP core is called through the Diamond development platform of Lattice Company,so that the data in the RAM is quickly stored to DDR2 in.When the display needs to display an image,the microcontroller controls the FPGA to read out the corresponding image data in DDR2,processes it through the interpolation algorithm,and outputs it to the video conversion chip Sil9022 to complete the conversion of the output signal,and finally displays it on the display.At the same time,the microcontroller reads the resolution information of all input videos from the FPGA every second through the IIC bus and calculates the latest display parameters in real time,and returns to the FPGA to execute,so that the display image can be real-time with the change in the resolution of the input video Adjustment.The system supports simultaneous input of 8 channels of up to 1920 × 1080 resolution video and simultaneous output of 9 channels of 1080 P video signals.The output video images can be combined into a 3 × 3 mosaic display matrix with a combined resolution of 5760 × 3240.Through simulation verification and experimental result display,the function of adaptive display of input video is basically realized.