Research On LDPC Codes Parallel Decoder Under Multi-core Technology

The Low Density Parity Check(LDPC)codes are a class of linear block code proposed by Gallager that can achieve performance close to Shannon limit.In recent years,with the rapid development of digital video media and the higher demand of digital communication systems for data transmission rates,LDPC codes parallel decoders have gradually become a new hotspot in research work.Designing LDPC codes parallel decoder based on FPGA and GPU are two common hardware solutions,but they have disadvantages such as high cost and poor flexibility.In this thesis,Quantization Min-Sum(QMS)parallel decoder and Alternating Direction Method of Multipliers(ADMM)parallel decoder based on multi-core general purpose processor are designed.The main research contents are as follows:1.The system model of digital communication and the basic knowledge of LDPC codes are summarized.And then the maximum likelihood decoding method for linear block codes and the sum product decoding algorithm for LDPC codes are elaborated.Moreover,The parallel architecture of multi-core CPU and the common multi-core parallel programming mode are emphatically analyzed.2.By making a detailed analysis of the Min-Sum(MS)decoding algorithm for LDPC codes,the QMS decoding algorithm with low memory requirements is designed.The simulation results show that the QMS decoding algorithm can obtain almost the same decoding performance as the MS decoding algorithm by selecting the appropriate quantization schema.3.For the QMS decoding algorithm,the frame-inner parallel decoder and the frame-inter parallel decoder for LDPC codes are designed by processor-level parallel method.And the instruction level parallel decoder for LDPC codes is designed by using SSE/AVX instruction set.Simulation results show that these three parallel decoders can significantly improve the decoding speed of LDPC codes compared with the serial QMS decoder,in addition,the instruction level parallel decoder can obtain the speed-up factor far superior to the other two parallel decoders,and the acceleration effect is much better.4.An approximate projection algorithm based on Lookup Table(LUT)can reduce the complexity of ADMM penalized decoding.In order to further simplify the search process of LUT entry index,a Hash-based index search method is proposed.By analyzing in detail the parallelizable structure in the ADMM penalized decoding algorithm,the frame-inner parallel decoder and the frame-inter parallel decoder for LDPC codes are designed.The simulation results show that these two parallel decoders can significantly improve the throughput of LDPC codes compared with the serial ADMM penalized decoder,and the acceleration effect of the frame-inter parallel decoder is better than the frame-inner parallel decoder.