Font Size:
a
A
A
Keyword [Min-Sum Decoding]
Result: 1 - 14 | Page: 1 of 1
1.
FPGA Implementation For Encoder And Decoder Of Quasi-Cyclic Low-Density Parity-Check Codes
2.
The Dvb-t2 Standard Ldpc Encoding And Decoding Dsp To Achieve
3.
Research On Key Technologies Of Construction And Decoding For LDPC Codes In Deep-space Communication
4.
Ldpc Code Decoding Technology Research And The Fpga Implementation
5.
Optimization Of Decoding Algorithm And Decoder Design For Ldpc Codes
6.
Coding And Decoding Algorithm For LDPC Codes And Its Implementation
7.
Research On LDPC Decoding In NAND Flash Memory Based On Soft-Information Sensing Strategy
8.
Construction And Decoder Design Of LDPC Code Based On Replacement
9.
Research On QC-LDPC Decoding Technology In Weak Turbulence Channel
10.
Study On Decoding Algorithms Of Low-density Parity-check Codes For MLC Flash Memories
11.
Research On Efficient Decode Algorithm For Multilevel Flash Memory Channel Fusing Priori Information Distribution
12.
Research On Extended Min-sum Decoding Algorithm Of Non-binary LDPC Code
13.
Research On LDPC Codes Parallel Decoder Under Multi-core Technology
14.
Research And Implementation Of Key Technologies Of SDR Based Air-ground Cooperative Broadband Wireless Communication
<<First
<Prev Next>
Last>>
Jump to
