The Study On ESD Device And Protective Circuits In Nano Integrated Circuit

Electrostatic discharge?Electrostatic Discharge ESD?has become one of the main prob-lems affecting the reliability of integrated circuits.With the rapid development of today's IC manufacturing industry,the feature size of devices has reached the nanometer level,and the emergence of new processes has brought more severe challenges to ESD produc-tion.ESD protection.Electrostatic discharge now is a problem that cannot be ignored.Therefore,learning of nano-scale ESD protection characteristics is an important topic.This paper is based on the research of ESD protection of nano-integrated circuits.The main re-sults are as follows:Firstly,the effects of ESD protection devices and processes are studied.Diode,MOSFET,SCR and improved structural modeling analysis are analyzed in Sentaurus.The forward conduction characteristics of the diode are better than the reverse conduction,but the for-ward conduction diode used as the ESD protective device is likely to bring the problem of low trigger voltage.In the two working modes of the MOSFET,the lateral parasitic tran-sistor conduction mode has higher efficiency and better heat dissipation.Therefor GGNMOS is a commonly used as ESD protective device.The turn-on voltage of the SCR device is too high,and the keeping voltage is too low.On this basis,the structure is im-proved,and the MLSCR and LVTSCR devices are proposed.The simulation results show that the LVTSCR solves triggering and turning on voltage problems,and has the ad-vantages of strong robustness and wide application range.The new processes gives chal-lenges to ESD design.Therefore,another focus of this chapter is to study the impact of new processes on ESD protection performance,and to cause ESD protection,such as LDD,STI,EPI,shallow depth,and Silicide.The device performance changes were systematical-ly analyzed,and corresponding improvements were proposed through simulation.Secondly,the performance of bulk silicon FinFET as ESD protection device is studied,and the relationship between the change of device structure size and protection performance is analyzed.FinFET has more device structure size parameters than traditional planar devices.Analyzing the parameter of the gate length L_g,Fin width W,Fin height H,gate drain dis-tance L_d,gate source distance L_s and number of Fin on the protective performance.Be-cause the increase of the gate length L_g makes the transistor Gain?decrease in the parasit-ic lateral,the secondary failure current decrease,and the trigger voltage is also increased due to the increase of the on-time;the increase of the gate-drain distance L_d causes the on-resistance R_on and the failure Current I_t2 to increase;The increase of Fin wide W has the greatest influence on the failure current.These three parameters have great influence on the ESD protection performance of GG-FinFET.At the same time,the optimization scheme and design strategy are proposed for the specific device design.Finally,the ESD protective circuit and early warning circuit are studied.The designed new ESD protective circuit uses the idea of two-stage RC time constant to separate the func-tions of ESD detection and holding time functions.Compared with the traditional RC trig-ger circuit,the layout area and false trigger are optimized,the area of layout is reduced to20%,the false trigger time is reduced to 100ns;The warning circuit designed for the clamp transistor is extracted and analyzed with the threshold voltage as the sensitive parameter.When the threshold voltage drifts more than 10%,an early warning is made,and all the above circuits are verified under the Cadence software,and the functions of the ESD mod-ule required by the project were completed.