Font Size: a A A

Research On Electrostatic Protective Devices And Protective Nets Of Deeply Micron

Posted on:2017-08-23Degree:MasterType:Thesis
Country:ChinaCandidate:L Y AiFull Text:PDF
GTID:2428330569498751Subject:Software engineering
Abstract/Summary:PDF Full Text Request
ESD(Electro-Static Discharge)in everyday life everywhere,according to statistics ESD on the integrated circuit(IC)losses as high as 58%,it has become the biggest factor affecting the reliability of integrated circuits.In this paper,the research of ESD protection device and protection network based on deep submicron process is carried out.The working mechanism of the ESD protection device under deep submicron process,the different device structure and different device parameters on electrostatic protection are studied.Voltage clamping circuit is the most important part of ESD protection network,this paper presents a new dynamic voltage clamping circuit,which is faster than the traditional dynamic voltage clamping circuit to open,discharge static current for a longer time,and layout area is only half of the latter.In this paper,ESD protection network of passive UHF RFID tag chip and lithium battery protection chip are designed in deep sub-micron process.Electronic tag chip is a typical digital,analog,radio frequency hybrid chip,through the voltage clamping circuit design in the different power domain interface,eliminating the need for static voltage clamping circuit between different power domains,the test results show that the whole Chip ESD protection capacity of more than 3KV.Lithium battery protection chip using deep submicron BCD(BIPOLAR CMOS DMOS)process design,the chip voltage range of 5V ~ 22.5V,the chip V1 ~ V5 port using low-voltage isolated PMOS and NMOS tube stacking design,the whole chip ESD protection network design is facing great challenges.Based on mastering the ESD protection principle and based on the ESD testing method of chip level and the practical engineering experience,this paper presents a new ESD protection network.
Keywords/Search Tags:ESD, standard CMOS process, Electrostatic discharge, layout, BCD process
PDF Full Text Request
Related items