Design On High Performance AES-GCM Cryptographic Circuit And Research On Hardware Trojan Detection Method

With the increasing demands of access network security and bandwidth,AES-GCM encryption authentication algorithm is used to resist potential security threats such as eavesdropping and counterfeiting.At present,the high-speed hardware implementation of this algorithm excessively pursues high data throughput and neglects the area overhead,but the highly competitive markets requires chips to have both high data throughputs and small area.At the same time,the security research of AES-GCM circuit rarely considers the threat of Hardware Trojan(HT).Once the key information in cryptographic chip is leaked by HT,it can cause serious consequences.Therefore,it is of great significance to explore the high performance implementation of AES-GCM cipher circuit and HT detection method.This paper mainly focus on the high performance AES-GCM cipher circuit supporting HT detection.Firstly,the principle of AES-GCM algorithm is analyzed,and a high performance AES-GCM cipher circuit implementation scheme is designed considering throughput and area.In order to solve the problem of low performance caused by low throughput and high area occupancy of serial and parallel architectures respectively,DACSE and Mastrovito algorithms are used to optimize the area of AES encryption part and finite area multiplier part.Meanwhile,pipeline partitioning method based on delay analysis is used to improve data throughput.Finially,we realize a high performance AES-GCM cryptographic circuit.In order to study the perniciousness of HT to AES-GCM encryption chip,we have analyzed the principle of fault attack.Design a HT which have the function of fault attack,and successfully leak the 10 th round key of AES.Finally,in order to detect the HT,based on the injection depth of the fault attack and the principle of the ring oscillator,a detection circuit for the HT is proposed.With less area consumption,a high performance AES-GCM cipher circuit supporting the hardware Trojan detection is realized.The high-performance AES-GCM cipher circuit designed in this paper can achieve 39.2 Gbps,occupy 5508 slices of resources and 7.06 Mbps/slices after integration with ISE 14.4 software platform.Compared with the existing serial circuit,the performance is improved by 68.5%.In addition,area of 4-degree parallel circuit with unoptimized is reduced by 70.2% and the performance is improved by 1.67 times.Furthermore,our results reveal that proposed countermeasure method utilize 0.274% increase in total area for AES encryption algorithm for detection of HT.