Research On Extremely-Low Jitter Synthesizer Based On Dual Plls

With the rapid growth of wireless communication technology,the requirements of RF technology are more stringent.Frequency synthesizers,as a fundamental module in RF receivers and transceivers,lay great influence on the system performance.As one of the research concern,jitter elimination in fractional-N synthesizers has been discussed warmly these years.Jitter elimination technique based on dual-PLL is the main research topic in this thesis.The research background,similar technique home and abroad and final research objective are given in chapter one.Then,fractional-N PLL,as the basis of dual-PLL,is introduced both in the basic structure and model establishment.The spec of fractional-N PLL will be discussed separately so as to link to the corresponding module,facilitating the design of dual-PLL system and modules.In Chapter three,the quantization noise caused in fractional-N PLL will be calculated and the cause will also be given.After the relationship between quantization noise and the parameters in PLLs is talked about,several mainstream quantization noise elimination methods are introduced in comparison with the proposed dual-PLL structure.In chapter four,the frequency plan,system design and actual realization are introduced,based on which every module of dual-PLL is analyzed in detail.A novel PFD/CP is proposed in dealing with the high reference frequency as well as the structure of other key modules.In chapter five,the simulation result of dual-PLL is proposed.Realized in TSMC 0.18 ?m technique,the dual-PLL system finally meets the frequency output range of 3-4GHz in post-sim.Besides,the settling time is measured 32 us in total,which is far less than 50 us in spec.When it comes to the most important index,clock jitter,the final value is 136.78 fs,which satisfies the 223 fs spec.