Research On The High-speed Serial Signal Jitter Problem Of Radar Signal Processing System

With the continuous development of signal acquisition technology, the amount of data radar signal processing systems need to handle is increasing, which put forward higher requirements for data transmission bandwidth and delay of the system. The interconnect structure which most of the existing radar signal processing system adopts are based on shared parallel bus. There are some disadvantages about this structure, like narrow transmission bandwidth, high transmission delay and a lot of pins are needed. It is not conducive to the expansion of the system in the future. In order to improve the performance of the system in data transmission, the architecture of high-speed serial interconnection is introduced by this paper, and research is carried out for solving the problem of signal jitter which occurs frequently in interconnected system.We analyze the requirement of signal transmission bandwidth in real-time radar signal processing from the perspective of the radar signal processing, and make a comparative analysis among three different signal transmission structures of the radar signal processing system. To reduce the impact to the system performance generated by data transmission, we introduce the high-speed serial interconnect structure.We study the factors that affect the signal jitter in the high-speed serial interconnect system and analyze the impact on jitter generated by channel loss, bias and unbalanced differential. We made a lot of simulations to quantify the impact of different parameters, which provides significant foundation for engineers to design circuit and select parameters.To solve the inter chip interference of the high-speed serial interconnect system, we study the equalization techniques of it. The paper analyzes the pre-emphasis, linear equalization and non-linear equalization in details. Through simulating we learn the inhibition by various equalization techniques to jitter. Besides, based on the theoretical analysis above, we simulate the pre-emphasis circuit and continuous linear equalizer to determine the parameters of the built-in high-speed serial transceiver Xilinx, and the jitter is reduced from 63 ps to 16 ps.In order to find out the cause of signal jitter more accurately, and optimize the error free sampling interval of high speed serial signal, this paper investigates the decomposition technique of dither signal. Reserch on the decomposition of the jitter based on Tail-Fit algorithm and FFT algorithm is carried out, and a decomposition method based on the overall experience of jitter decomposition(EEMD) is proposed. Simulation on different point analyses the efficiency of the performance of various algorithms on jitter decomposition, and the results of the simulation show that the decomposition method based on EEMD algorithm proposed by this paper has higher accuracy.