Design And Verification Of Circuit To Gauge Standard Cell Delay Timing

As integrated circuit process characteristic size(poly minimum size)reached micron even deep-submicron order,the scale of circuit becomes bigger and bigger,the integration and complexity is also improved.In order to improve efficiency,reduce design cycle,ensure the silicon success in the first time,Standard cells,which were silicon proven,have been widely used in integrated circuit.Now HHGrace,which is the biggest 8 inch wafer foundry,has proposed HHGrace 90 nm E-flash standard cell library.The library will be widely used in SIM card?Ukey?SWP and so on.In order to verify the library timing accuracy and model precision of simulation,the thesis takes standard cell INV?NAND ?NOR as tested circuit.Firstly,introduce the foundation of standard cell library flow,especially high-light the design and verification about circuit to measure standard cell delay timing.The thesis considered some factors such as measured circuit design?layout design,parasitical parameters extracted and tested data versus simulation data.Firstly,circuit design.The thesis proposes a novel circuit to measure standard cell delay timing precisely.It offsets delay timing of measured circuit itself by offsetting device and path delay.The circuit measures input signal directly,avoiding measuring output signal,which maybe brings in apparatus loading.Secondly,design layout.The thesis not only offsets device and path delay but also balances power and ground voltage everywhere.It also includes the signal shielding,which avoids disturbance and shrinks parasitical loading.Thirdly,extract parasitical parameters.The thesis considers HHGrace 90 nm E-flash process platform factors,calculating parasitical parameters such as WPE,NRD/NRS,parasitical resistor,parasitical capacitor and parasitical diode distribution.Finally,MPW(multi project wafer).The thesis compared the tested data and simulation data at different process corner.The result demonstrates conclusion that the tested data is 3% bigger than simulation data,the difference tendency is one direction.The thesis verified the accuracy of simulation model and provided the basis for the circuit timing revision.