Design Of D Flip-Flop Applied To Array-type Time To Digital Converter

As the basic of digital integrated circuit sequential elements, the D-type flip-flops (DFF for short) affect the performance of the whole system. The performance of the traditional DFF sampling precision, working speed and area seriously limits the counting accuracy and range of the TDC system thus cannot satisfy the requirement for special applications of the system.Setup and holding time and transmission delay parameters have been modelled, meanwhile the theory basis of dynamic DFF characteristics are given in this thesis. In view of the different application requirements of the TDC, two kinds of DFF circuit structure are necessary. One is for high speed, low power consumption, compact area master-slave type, which are used to implement the function of coarse count of TDC. The other one is for low-setup and holding time sensitive amplifier tyepe used to complete the fine count TDC which requires high precision sampling. The balance of sampling precision, speed, area, and power consumption has been achieved. The scheme of reducing rag effects of TSPC circuit has been given. The half static master-slave type DFF improvement and design work has been finished. The circuit design of the chip test scheme for DFF characteristics is put forward. Not only DFF function can be verified but the performance of its dynamic characteristics is tested by the scheme.Based on TSMC 0.35um CMOS process, the designed DFF circuit is achieved through pre-simulation, layout drawing, post-simulation and tape-out by Cadence EDA tools this paper. The simulation results show that the setup and holding time of the classical dynamic master-slave type DFF is 85ps, and the transmission delay is 264ps. The values of the sensitive amplifier shape SAFF are 120ps and 407ps respectively.The value of the half static master-slave type DFF is 85ps which has decreased 60 percent while the area is 29.8×13.6? m2, which has decreased 18%. Compared with the classical dynamic master-slave type circuit, the covers the area of 12.775×13.6? m2, while the consumption is 11.31 ?.A@125MHz which decreased 40,48 percent respectively. The test results show that the setup and holding time of TSPC is 162ps, meanwhile the transmission delay is about 340ps. The parameters of the TPSC3 are 298ps and 395.5ps. Chip test results show the consistence with the simulation and the design meet the requirements of the system.