Design And Implement Of Heterogeneous Multi-core DSP Based On Costar Ⅱ

With the development of communication and multimedia, high performance processors are desired urgently. At the same time, single core processors are hard to meet the growing demands of application because of the limitation of its complexity and power. With the development of integrated circuit technology, Multi-core on chip processors are growing as a new trend.A heterogeneous multi-core DSP architecture is proposed based on CoStarII DSP in this thesis. The multi-core DSP architecture integrates four simplified CoStarII DSP cores and a RISC CPU core. Each core has its own local memory. All the cores can access data shared memory, and the four DSP cores can use program shared memory dynamically. Furthermore, all the cores hold several synchronization and communication mechanisms, such as mailboxes, semaphores and interruptions.In order to implement the multi-core DSP architecture, the contents of this thesis mainly includes the following aspects: (1) Based on the study of multi-core system, the CoStarII DSP is condensed to simplified DSP core. (2) The local program memory and local data memory are designed. (3) The program shared memory which can be dynamically allocated for DSP cores as local program memory and can also support sharing subroutines among the DSPs is designed. (4) The data shared memory with parallel multi-bank structure is designed, which can be accessed in parallel by all the cores. With mailboxes or semaphores, the data shared memory can change datum among all cores fast. (5) A communication system with blocking mailboxes is proposed, in which there are a couple of mailboxes between any two cores. The blocking mailboxes can not only transfer important datum among cores but also do automatic synchronization by blocking operations which is a way of low power. (6) An interrupt mechanism among cores is designed. (7) The usual methods of task assignment and programming models according to the multi-core DSP are described. (8) The JPEG parallel decoding is implemented in the multi-core DSP and verified in FPGA validation platform. The results show that the multi-core DSP is easy to program and efficient for parallel tasks. The results of DC synthesis show that the scale of the multi-core DSP is equal as three million gates.