The Design Of Digital Signal Processing Unit In Sigma_Detla ADC

?_?ADC,as a branch of ADC,has been widely used in the field of mixed signal processing due to its high precision and low noise.Typical?_?the main functions of the ADC module contains the analog modulator and digital sampling filter.The current domestic research on?_?ADC focus on improve the performance of the front-end modulator,but foreign related products not only have small size,low power consumption of digital sampling filter,and also integrated with multi-function digital interface,can through the function of the digital interface configuration ADC chip.The objective of this paper is to design a post-digital processing unit of?_?ADC.This digital processing unit not only has a digital filter with the output digits of 24bit,but also has a multi-functional digital serial interface,which can regulate the output rate,effective edge,and even the gain of PGA?Pmgrammable Gain Amplifier?before the modulator.The area and power consumption of the?_?ADC mainly depend on the digital filter in the digital signal processing unit.Therefore,while realizing the functions,this project also optimizes the signal processing unit to minimize the cost of hardware.The digital filter uses a three-level cascade structure.The first level is CIC?Cascaded integrator-comb?filter with a recursive structure,whose extraction factor varies between2⁵,2⁶ and 2¹² in order to have a variable output rate.The second level filter is CIC compensation filter,which completes the decay of the pass band of the CIC filter of the first level and completes the decimation of twice.The third stage filter adopts FIR low-pass filter.The filters of the latter two levels adopts the efficient structure of polyphase decomposition technology,adopt the low and symmetric order structure,and adopt the optimization coefficient of CSD?Canonic Signed-Digit?coding.These optimization methods effectively reduce the chip area and power consumption.The digital interface adopts SPI serial interface.The SPI interface of this project has read-write function.Based on the simulink tool of the maltab,the behavior-level model of digital filter is modeled.The excitation signal is given by code,and the overall passband ripple of the filter model is about 0.006db.The PSD of the behavior-level model under each extraction factor conforms to the expected value.Then,verilog was used to complete the establishment of RTL level filter,and the design of clock module,SPI interface and host module was completed.Moreover,joint simulation was conducted.When the system extraction factor was 128,Fs for 2048 KHZ,the SNR output of simulation was 124.7db,unchanged compared with the SNR of input signal,and the maximum output rate was16kHz.In the 0.35 m 5V standard CMOS process,the RTL level of the code using DC logic synthesis.SoC Encounter software is used to complete the layout design of the chip,the area of layout is 3.2×3.25mm².And then the simulation verification of layout and wiring is carried out.When the extraction factor is 128,the SNR of the output data obtained after simulation is still 124.7db.