Research And Design Of The Modulator And Digital Decimation Filter In Sigma-Delta ADC

With the rapid development of digital signal processing technology,the demand for high-performance ADCs as the interface between analog and digital is becoming more and more urgent.Sigma-Delta ADC,with its unique sampling mechanism and noise-shaping method,has been widely used in the field of high-precision analog-to-digital conversion such as digital audio,data acquisition and so on.Nowadays,a fully functional Sigma-Delta ADC mainly includes anti-aliasing filter,pre-programmable amplifier,Sigma-Delta modulator,digital decimation filter.This thesis mainly focuses on the latter two modules.Firstly for the modulator,on the basis of in-depth study and understanding of its principle,the overall parameters of 4^th order 128 times oversampling and 1-bit quantization are determined through systematic discussion and analysis,according to the design index of output SNDR higher than 100 dB and bandwidth of 24 kHz.A feedforward MASH structure is adopted for its stability,and the system-level ideal model of the modulator is designed based on Simulink.The advantages of the feedforward structure compared with the traditional one are qualitatively and quantitatively analyzed.After that,the system-level model of the ideal modulator is designed based on Simulink.Then,the non-ideal factors exist in actual circuit are deduced and modeled in detail,the design parameters of the key modules of the modulator are obtained by scanning simulation method and the modulator model including non-ideal factors is built.Then under the guidance of the system-level simulation,the circuit level implementation of the modulator is presented based on SMIC0.18?m technology,which mainly includes the design and optimization of the integrator,operational amplifier,quantizer,and digital noise cancellation logic.The final simulation results presents that the SNDR of the modulator output is 103.59 dB and the ENOB achieves16.92 bits.Aiming at the problem of large area and power consumption of the digital decimation filter under the circumstance of high input bit-width,this thesis chooses reasonable parameters and adopts multi-stage cascade method to reduce the overall order of the filter in system level.In terms of structural design,a second order linear phase FIR filter is introduced at the tail of the CIC filter,which can compensate the pass-band performance at a lower cost,and reduce the attenuation at the edge of the pass-band from nearly 0.8dB to about 0.01dB.The subsequent decimation and filtering work is completed by two halfband filters,and the poly-phase branch symmetry method is used to optimize their implementation structure,which further reduces the total number of coefficients.An improved CSD coding method is adopted to encode the coefficients during the RTL level code implementation,and the multiplication operation is converted into the least-order addition operation,which realizes the filter structure without multipliers and reduces the complexity of the circuit.Finally,through behavioral level simualation,RTL level simulation and DC synthesis,the correctness of the digital decimation filter and optimization method are verified.Finally,the modulator and digital decimation filter are combined and simulated in Cadence environment.The results provide that under the conditions of 4.875kHz input signal frequency,6.144MHz sampling frequency and 128 times oversampling rate,the SNDR of the overall output is 102.69dB and the ENOB are 16.77 bits,meeting the design requirements.