The Design And Implementation Of High-Speed Packet Identification

In recent years,with the rapid growth of network users' demands for network services and quality,high-speed network transmission and diversified data packet types bring new challenges to the switches.Packet identification is one of the main functions of a switch.Its purpose is to identify data packets in the network and provide more accurate services according to the type of data packets.With the advent of 40 / 100 Gb Ethernet standards,the ever-growing need for forwarding rates presents new challenges for the switch's forwarding performance and hardware design.At the same time,the emergence of Software Defined Network makes the network more flexible.The OpenFlow protocol is the most important southbound interface standard in the current SDN technology.The OpenFlow protocol specifies 44 match fields,which greatly increases the number of fields to be identified by the switch.The challenges faced by the packet identification can be summarized as follows: 1)the packet identification should conform to the 40 / 100 GbE standard;2)the packet identification should handle diversified flow types;3)save the occupied storage space.Based on the above analysis,this thesis first analyzes the current research status of packet identification at home and abroad and summarizes the advantages and disadvantages.The related background technology is emphasized: a bit-based stride BV method.Secondly,based on the background technology,a matching method suitable for range fields is proposed.The method is an improvement of the bit vector method.Thirdly,a high-speed packet identification method that supports multi-field matching is proposed.In the solution,the information in the data packet is divided into the information suitable for range matching and the information suitable for other matching modes,then the information suitable for the range matching is matched with rules by the proposed method,and the information suitable for other matching modes is matched with rules by the stride BV algorithm of two-dimensional pipeline architecture.Then a bit-wise logical AND operation is performed between the results to get the final matching result.This search scheme is suitable for matching any type of information in a data packet,but has the disadvantage of taking up much storage space.Fourthly,in view of the above-mentioned shortcomings,improvements are made.Our improved scheme is that divide the ruleset into multi-level flow tables,each flow table only stores the information of one field or several fields,and does not store duplicate information.This solution effectively saves the storage space of the packet identification.Finally,the proposed algorithm is implemented in verilog HDL language,simulated by Xilinx vivado software,implemented on Xilinx ZedBoard FPGA board.In summary,this thesis proposed a storage-optimized high-speed flow recognition algorithm that supports multiple types of fields.According to the theoretical analysis and board-level verification results,the advantages of this algorithm are as follows: 1)the huge ruleset is divided effectively to save the storage space;2)the processing speed can reach 100 Gbps;3)suitable for multi-field matching and adapt to the development and changes of the rule set.Our goal in the future is supporting dynamic updates and achieving higher frequency.