A High-throughput Hardware Implementation Of XTS-AES Encryption Algorithm

In recent years,with the increasing popularity of personal computers,disk and tape drives,the loss of sensitive personal data is becoming an increasingly serious problem.To address this issue,IEEE 1619 secure storage Committee(SISWG) in April 2008 formally announced the XTS-AES standard algorithm,which is a new encryption mode for high performance RAID applications, solid-state hard drives and Fibre Channel ,as to slove data encryption issues of the block-oriented storage devices.This paper first in-depth analyzes the XTS-AES algorithm description and application environment,and compared with some IP company's XTS-AES encryption module in the area,performance advantages and disadvantages,and then foucs on improving the throughput,this paper implements the XTS-AES hardware encryption circuit with full-pipeline structure and optimized modular multiplication module. In the design,the proposal increases throughput by unrolling the data path.Meanwhile,it also improves the circuit clock frequency and overall perfprmance by using inner pipelined structure to optimize the critical path.In this dissertation, the XTS-AES encryption circuit is described with Verilog HDL.The function simulation and FPGA verification are performed by using EDA tools. The simulation results show that the design meets encryption function of XTS-AES.Using UMC 90nm CMOS standard cell library to complete the synthesis, analysis show that the scale of the whole design is about 203K equivalent gates, the maximum operating frequency is 262MHz, scheduled to meet the design requirements.