Research On Critical Technology Of 10-Gigabit Ethernet Protocol Conversion

With the development of network communication technology,higher requirements are placed on the data transmission speed,and various communication protocols are proposed according to different requirements.The need to communicate with each other using devices of different protocols is increasing,so special protocol conversion devices need to be designed to achieve this.his paper is based on FPGA design of the 10 Gigabit protocol conversion system,which realizes the conversion between standard Ethernet protocol and dedicated link protocol.After analyzing the specific design requirements,the corresponding engineering implementation methods are given.The specific work includes the following aspects:1)Study the Ethernet standard communication protocol,and use the Xilinx Ethernet IP core combined with the FPGA internal logic to design the Ethernet interface receiving and transmitting controller to realize the transmission and reception of Gigabit Ethernet low-speed data and 10 Gigabit Ethernet high-speed data;2)Study the system-specific link protocol,realize the multiplexing/splitting function of high and low speed data through FPGA internal logic design protocol converter,and realize the conversion between standard Ethernet protocol and dedicated link protocol;3)Research high-speed serial transmission technology,and design high-speed serial communication controller based on Aurora protocol through Xilinx Aurora IP core combined with FPGA internal logic to achieve data transmission rate of 10 Gbps data;4)In order to ensure the high efficiency and real-time performance of high-speed data processing,the Xilinx FIFO IP core is combined with the FPGA internal logic design data cache processor to realize the buffering and processing of 10 Gbps data.Functional simulation and board level verification were performed on the functions of each module,and the generated bit stream file was downloaded to the FPGA hardware development platform for actual system testing and joint debugging.The system was tested with the network tester and supporting software.The test results verified that the module design meets the functional and performance requirements.