Design Of Reluctance Rsolver And Decoder

Reluctance resolver is widely used in aviation,new energy vehicles and other fields due to its small size and strong anti-interference,but its accuracy is insufficient compared with ordinary winding resolver.In this paper,the working principle of two kinds of output-winding winding reluctance resolvers was analyzed firstly.Then through the simulation calculation,the output waveform of the reluctance resolver of the sinusoidal output winding and the equal coils output winding is obtained under the same size of the rotor and stator.The envelope curve is extracted from the output waveform and Fourier decomposition is performed to obtain the harmonic content and distortion rate of each resolver.According to this,the accuracy of the two kinds of different output winding reluctance resolvers is verified.Finally,the reluctance resolver with higher output accuracy is optimized to further improve its accuracy,and a prototype of a reluctance resolver is fabricated.The precautions for winding and the compensation of the lead wire are proposed.The application of the resolver must be combined with its decoder.The function of the decoder is to convert the analog signal of the resolver into digital signal and then calculate the rotor angle and speed.Since the dedicated decoder chip is expensive and limits the use of the resolver,in order to ensure the decoding accuracy and reduce the cost of the decoder as much as possible,it is a feasible method to build the decoder of the resolver by using the separation device.In this paper,the Field Programmable Gate Array(FPGA)is used as the decoding core chip of the decoder.The direct digital frequency synthesis(DDS)technology is used together with the D/A converter to generate the excitation signal required by the resolver,thus constructing the resolver decoder.Compared with the dedicated decoder chip,the decoder can be multi-channel synchronous decoding in principle,which can greatly save costs.Depending on the powerful parallel processing speed and hardware operation mode of FPGA,this paper adopted Coordinate Rotation Digital Computer(CORDIC)algorithm to solve the resolver angle,and CORDIC algorithm was improved according to the actual operation.An experimental platform was built to verify the performance of the decoder.The experimental results show that the designed decoding system can basically meet the requirements of accuracy and response speed.At the end of this paper,the error of the experimental results was analyzed,the source of the error is determined and the compensation method is proposed to further improve the decoding accuracy.