Research And Implementation Of Multiprocessor-based On-chip Cache Sharing Strategy

With the rapid development of information technology,the scale and complexity of software have increased significantly.This poses a great challenge to the performance of computer systems.The performance of traditional uniprocessor architectures has encountered bottlenecks such as increased power consumption and limited parallelism.It has been difficult to adapt to large scale application scenarios.The chip multi-processor architecture can improve the parallelism of tasks including process-level parallelism and thread-level parallelism,resulting in significantly improved computing performance.Today,multiprocessor architectures have become the mainstream of processor architecture development.In a multi-processor architecture,the last-level on-chip cache is often shared among multiple cores to provide each core with a large amount of cache storage space to reduce the access to off-chip data.However,since the shared cache can be accessed by multiple cores,accessing to the cache of one core may replace data of other cores,which ultimately results in degraded processor performance.An effective sharing strategy for the shared cache can avoid this problem to some extent.At the same time,due to the high cost of hardware replacement of LRU(Least Recently Used)replacement algorithm,the pseudo-LRU replacement algorithm is used in many real processors.Based on this,this paper proposes a shared cache partitioning mechanism based on the binary tree pseudo-LRU replacement algorithm.This paper proposes a shared cache partitioning mechanism based on binary tree pseudo-LRU replacement algorithm.Compared with the analysis based on LRU replacement algorithm,the hardware implementation complexity can be reduced.The partitioning mechanism adopts a record dividing edge to reduce the number of flag bits of the processor to which the cache belongs,and according to the characteristics of the binary tree in the partitioning mechanism,the number of counters used by the single partitioning unit in the monitoring module is reduced to half the original value,at the same time,this paper divides the shared cache into units.Subsequently,the partitioning mechanism was designed and implemented in the Multi2 Sim architecture simulator.The SPEC CPU2006 benchmark program test set was used to verify the partitioning mechanism.The SPEC CPU2006 benchmark program test set was used to verify the partitioning mechanism.The simulation results show that the partitioning mechanism based on the binary tree pseudo-LRU replacement algorithm proposed in this paper can increase computer performance by an average of 4.8%.Finally,this paper uses Verilog language to model the key modules of the partitioning mechanism.A randomized test platform is built to randomize the partitioning mechanism and the results can be automatically compared.The results show that the related circuits are functionally correct.